Method and system for data and timing recovery in a bi-phase coded data signal

ABSTRACT

For data and timing recovery in a bi-phase coded data signal (data), the data signal is sampled using a sampling frequency (2.5·fbit) which is greater than the double bit frequency (fbit) of the data signal (data). The bit limits of the data signal are then determined from the sampling values thus obtained and the data bits and the corresponding bit clock pulse (clock pulse) of the data signal (data) are recovered from said limits.  
     Zur Daten-und Taktrückgewinnung bei einem biphase-codierten Datensignal (Daten) wird das Datensignal mit einer Abtastfrequenz (2.5·fbit) abgetastet, die grösser als die doppelte Bitfrequenz (fbit) des Datensignals (Daten) ist; dann werden den so gewonnenen Abtastwerten die Bitgrenzen des Datensignals bestimmt und daraus schliesslich die Datenbits und der zugehörige Bittakt (Takt) des Datensignals (Daten) regeneriert.

FIELD OF THE INVENTION

[0001] The invention relates to a method and an apparatus for data and clock recovery in a biphase-coded data signal.

BACKGROUND OF THE INVENTION

[0002] There are two types of biphase codes, the so-called biphase mark code and the so-called biphase space code. In the biphase mark code, logical ones are specially coded, and, in the biphase space code, logical zeros are specially coded. In the biphase mark code, there is always a change of the logical states between the data bits of the data signal, and in the case of a logical one there is also a change in the data-bit middle, whereas there is not in the case of a logical zero. Lines A and B according to FIG. 2 show this relationship. Similar considerations apply to the biphase space code.

[0003] For data recovery of such a biphase-coded data signal, the bit clock needs to be recovered on the reception side. To that end, it is known to use a phase-synchronized clock generator (PLL), which is exactly locked to double the bit frequency of the data signal. At substantially high data rates, however, it is difficult to maintain the requisite accurate phase relationship between the clock frequency and the biphase data, which is necessary for reliable data decoding.

[0004] There is therefore a need to provide a method with which clock recovery for a biphase-coded data signal is possible even at substantially high data rates.

SUMMARY OF THE INVENTION

[0005] This need and others are addressed by the present invention, in which operation is carried out with an uncorrelated clock and, by means of the sampled values and by establishing the bit limits, the original data bits are regenerated from which the bit clock can then be derived in a straightforward way. Particularly accurate clock recovery, which is not susceptible to data jitter and to clock inaccuracies, is obtained when the phase-locked oscillator delivering the sampling frequency is synchronized with the biphase data recovered in this way.

[0006] A method according to the invention can be used for both biphase-mark-coded and biphase-space-coded data signals.

[0007] Still other aspects, features, and advantages of the present invention are readily apparent from the following detailed description, simply by illustrating a number of particular embodiments and implementations, including the best mode contemplated for carrying out the present invention. The present invention is also capable of other and different embodiments, and its several details can be modified in various obvious respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The invention will be explained in more detail below with the aid of schematic drawings with reference to an exemplary embodiment for a biphase-mark-coded signal.

[0009]FIG. 1 shows the block diagram of an apparatus according to the invention for carrying out a method according to the invention, and FIG. 2 shows the associated signal waveforms.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0010] The biphase-mark-coded data signal B, which is derived from the NRZ data signal A and is to be regenerated, is delivered on the reception side to a sampling circuit 1, downstream of which a detector 2 is arranged. The sampling frequency C for the sampling circuit 1, and the clock frequency for the detector 2, are delivered by a phase-locked oscillator 3 whose output frequency is selected to be 2.5 times as great as the bit frequency of the data signal B.

[0011] Using the sampling signal C of the oscillator 3, the biphase data signal B is sampled in the sampling circuit 1, and the sampled values D obtained in this way are delivered to the detector 2. In order to obtain as many sampled values as possible, sampling is carried out in the sampling circuit 1 with both the positive and negative edges of the sampling signal C. With 2.5 times the bit frequency as the sampling frequency, in theory five sampled values per data bit are obtained. Subject to effects such as data jitter and clock accuracy of the biphase data B, however, four or six sampled values D may also be obtained for one data bit. This is established in the detector 2. In this way, the bit limits E can be established in the detector from the successive sampled values D, since, according to the biphase mark code, a transition between zero and one implies either a change between the data bits of the data signal B or a change in the bit middle. Therefore, if the detector 2 establishes a change of the logical state one and zero in the tolerance range of from 4 to 6 sampled values, then this implies a logical zero in the regenerated data signal F, whereas if a change of the sampled values D is established in a substantially short interval, for example after just two logical ones, then this implies a one in the regenerated data signal F.

[0012] It is then possible to regenerate the associated bit-clock frequency G in a straightforward way from the thus regenerated data bits F of the original signal A. Both the data bits and the bit clock of the original data signal A are hence regenerated. The detector 2 may be configured with a very high tolerance and, in the exemplary embodiment, it is merely necessary for it to reliably recognize the bits with 4, 5 or 6 sampled values. The detector is therefore tolerant with respect to data jitter and clock accuracy. The data and clock recovery will be even more accurate if the oscillator 3 is synchronized with the bit clock G recovered in this way, as is schematically indicated by the active connection 4 in FIG. 1.

[0013] The serially regenerated data bits F, with the associated bit clock G, can subsequently be converted into parallel data in the known way by means of a serial/parallel converter 5, and the byte clock obtained thereby can likewise be used for synchronizing the oscillator 3, in the scope of the active connection 6 according to FIG. 1, in order to synchronize the sampling clock accurately with the biphase data.

[0014] While the present invention has been described in connection with a number of embodiments and implementations, the present invention is not so limited but covers various obvious modifications and equivalent arrangements, which fall within the purview of the appended claims. 

What is claimed is:
 1. Method for data and clock recovery in a biphase-coded data signal, characterised in that the data signal is sampled using a sampling frequency which is greater than double the bit frequency of the data signal, the bit limits of the data signal are determined from the sampled values obtained in this way and the data bits and the associated bit clock of the data signal are then regenerated therefrom.
 2. Method according to claim
 1. characterised in that the sampling frequency is selected to be 2.5 times as great as the bit frequency.
 3. Method according to claim 1 or
 2. characterised in that the clock generator generating the sampling frequency is synchronised using the regenerated bit clock.
 4. Method according to one of the preceding claims, characterised in that the regenerated serial data signal is parallel-converted and the clock generator is synchronised using the byte clock obtained in this case.
 5. Arrangement for carrying out the method according to one of claims 1 to 4, characterised by a sampling circuit (1), a phasesynchronised oscillator (3) generating the sampling frequency (C) with a sampling frequency of at least 2.5 times the bit frequency, a downstream detector (2), which is clocked with the sampling frequency (C) of the phase-locked oscillator (3) and in which the bit limits (E) of the data signal are determined from the transitions of the sampled values (D) between the logical states (zero, one), and the data bits (F) and the associated bit clock (G) are then regenerated therefrom. 